This invention relates to integrated circuitry and more particularly to an improved integrated circuit chip assembly.
Integrated circuit (IC) technology is central to electronics systems in use today because it improves system reliability, increases system performance and decreases system size, weight, power and cost. An integrated circuit is an interconnected array of active electronic devices, such as transistors and diodes, with passive components, such as resistors and capacitors, fabricated from a single crystal of semiconductor material bY etching, doping and diffusion. Throughout the discussion the term device will be used to describe active electronic devices while the term component will be used to describe generally both active devices and passive components An integrated circuit chip is capable of performing at least one and sometimes many complete circuit functions.
Of major concern to integrated circuit chip assembly designers is the heat generated by the active electronic devices This is especially true with power devices. The overall chip design must provide a functional assembly but also must be designed to permit sufficient heat dissipation of the heat generated by the active electronic devices of the integrated circuit.
FIG. 1 shows the cross-section of a portion of a typical integrated circuit chip assembly 10 and shows one active electronic device 12 (encircled) and one microstrip transmission line 14. Throughout this discussion reference will be made to transmission lines but it should be understood that strictly speaking these are microstrip transmission lines. Microstrip transmission lines provide a microwave path and are used for the interconnection of the many components typically comprising an integrated circuit.
Generally, a typical assembly 10 is comprised of a substrate 16 made of a semi-conductor material such as silicon, silicon-on-sapphire (SOS), or gallium arsenide (GaAs). Substrate thickness is about 4 mils. The choice of the substrate material depends on the circuit properties required. In the assembly 10 across a first surface 18 of the substrate 16 a uniform dielectric layer 20 is deposited. A typical layer thickness would be about 0.004 to .008 mils. Note that while a substrate made from silicon or silicon-on-sapphire has an electrical resistivity on the order of magnitude of 10 ohm-cm and therefore requires a dielectric layer such as layer 20 for electrical isolation from transmission and component circuit lines, a substrate made from gallium arsenide, on the other hand, has a resistivity on the order of 10.sup.7 ohm-cm and therefore requires no such layer. This is illustrated in FIG. 2 and will be further discussed later. Referring again to FIG. 1, which could be an assembly using either silicon or silicon-on-sapphire as the substrate material, the transmission line 14 is deposited upon this dielectric layer 20 and therefore insulated only from the substrate 16 by this layer 20. A typical thickness for a transmission line would be about 2 to 4 mils. The electronic device 12, however, exists within and upon the substrate 16 and may utilize the dielectric layer 20 as a means to isolate elements of the electronic device 12. For illustrative purposes, the electronic device 12 is assumed to be a field effect transistor (FET) which during operation generates heat which must be effectively removed to avoid damage to the surrounding circuitry and to avoid degradation of the device itself. A cursory description of a FET, which is typical of heat generating electronic devices, will be provided.
For the FET shown as the electronic device 12 in FIG. 1, given a substrate 16 of a specific material such as silicon or silicon-on-sapphire, a dope additive, that is a specific impurity added to a pure semiconductor to give it required electrical properties, is introduced into the substrate to form a doped source region 22, a doped drain region 24 and a doped channel region 32. Generally the width of the FET is approximately 0.2 mil and the length extends across the face of the substrate, which is about 0.2 inches. To form the wires which supply power and also interconnect the FET, thin circuit lines 26, 28, 30 of electrically conductive material are deposited upon the first surface 18 of the substrate 16 and upon the surface of the dielectric layer 20. Thin films of deposited materials, such as the dielectric layer 20, are used to provide dielectric isolation between the circuit line 28 of electrically conductive material and the substrate 16. Generally the thickness of the circuit lines is approximately 0.08 to 0.16 mils. Note that circuit lines 26 and 30 contact the first surface 18 of the substrate 16. Selective removal of portions of the dielectric layer 20, which may be done using conventional etching techniques, are necessary for this. The doped channel region 32 exists in the substrate 16 between the doped source region 22 and the doped drain region 24. Characteristic of an FET, the resistance of the channel region 32 can be altered by appropriately altering the applied voltage, also known as the gate voltage, through circuit line 28. Based on the voltage through circuit line 28, a current supplied to circuit line 26 will pass from circuit line 26 into the doped source region 22 and through the doped channel region 32 to the doped drain region 24 into the circuit line 30. Current utilized for the operation of the FET generates a significant amount of heat, especially in the channel region 32, that must be removed in some manner and this goal is a significant factor in the overall design of an integrated circuit chip assembly.
In current microwave IC chip assembly designs, structural support of the assembly is provided entirely through the substrate 16 and as a result heat dissipation is hampered by the substrate thickness, which is structurally necessary. Furthermore a ground plane 34 is provided against a second surface 36 of the substrate 16 which may act both as an electrical ground and a thermal heat sink. Note the same substrate thickness that provides mechanical support also acts to space the transmission lines relative to the ground plane and this distance between the transmission lines to the ground plane strongly effects the impedance of the transmission line.
Addressing the substrate thickness relative to the effective heat transfer, absent a requirement for the substrate 16 to provide structural support to the chip assembly, much more flexibility would be available to adjust the substrate thickness to maximize heat transfer and to influence the impedance of the transmission lines. The substrate 16 minimum thickness would be limited only by the need to provide enough thickness for the doped source region 22, the doped drain region 24 and the channel region 32 to exist on the substrate 16. The transmission lines may then be spaced from the ground plane a minimum distance of the substrate reduced thickness and the maximum distance would be essentially independent of the substrate thickness. Theoretically, the substrate could then be reduced to a thickness of 1 or 2 mile from the typical thickness of 4 mils. For heat transfer between the electronic device 12 and the thermal heat sink in the ground plane 34, this small distance would be ideal. However, currently substrates are sized with considerable weight given to both the desired impedance of the transmission lines and the necessary structural support required for the entire integrated circuit chip assembly and this dictates a substrate thickness that may not be optimum for heat transfer requirements.
A design for the chip assembly is needed that permits the thickness of the substrate to be greatly reduced to enhance heat transfer between the electronic device and the ground plane but simultaneously provides the necessary structural support to the assembly.
Aside from the substrate thickness restricting heat transfer, a further disadvantage of current designs, as mentioned, results from the necessity to size the substrate 16 to adjust impedance of the transmission lines for the assembly. Because of this substrate thickness requirement severe limitations are imposed on the design parameters for the transmission line 14. For uniformity and compatibility with other circuits, the impedance of the transmission line 14 is often fixed by general convention of the circuit designers and it is imperative that the assembly be designed to satisfy this requirement. The impedance of the transmission line is determined by three factors - the electrical resistance of the transmission line itself, the electrical inductance caused from nearby conductors and the electrical capacitance resulting from the transmission line positioned relative to another conductor. Designing for a constant impedance in the transmission line 14 requires considering each of these three factors.
Generally, the resistance of the transmission line is a function of the width, thickness and material of the transmission line itself. The contribution of the transmission line resistance to the overall impedance therefore may be adjusted by altering the transmission line dimensions and material. On the other hand, the inductance of the transmission line is determined not only by the transmission line dimensions and material but by the distance of the transmission line to another electrical conductor, especially the ground plane. Similarly, the capacitance is determined by the distance to another electrical conductor, especially the ground plane and also by the dielectric substance between the transmission line and the ground plane. Subsequently, the impedance contribution from the inductance and the capacitance of the transmission line 14 is largely dependent on the distance from the transmission line to the ground plane and the dielectric constant of the substrate between the transmission line 14 and the ground plane 34.
Specifically, in the case of the chip assembly 10 in FIG. 1, the inductance of the transmission line 14 is directly effected by the distance from the transmission line 14 to the ground plane 34 while the capacitance of the transmission line 14 is effected by the distance from the transmission line 14 to the ground plane 34 and the dielectric constant of the substances between the transmission line 14 and the ground plane 34. In FIG. 1 the dielectric substance between the transmission line 14 and the ground plane 34 is a composite of both the substrate 16 material and the dielectric layer 20 material and subsequently the dielectric constant in this case will be a composite value determined by the dielectric layer 20 and the substrate 16 characteristics. The substrate 16 since it must provide structural support for the assembly typically must be of a thickness of about 4 mils. Because of this, the inductance and the capacitance of the transmission line 14 are essentially determined by the fixed thickness of the substrate 16. For that reason, the only flexibility in the transmission line 14 design for the assembly in FIG. 1 comes through adjusting the impedance by changing the width and the thickness of the transmission line 14. While this does change the overall impedance of the transmission line 14, the effects are not always desirable.
A design is needed for an integrated circuit chip assembly that provides structural support for the entire assembly but at the same time permits adjustment of the inductance and capacitance of the transmission line by moving the ground plane 34 nearer to or farther from the transmission line 14 and by depositing a dielectric substance between the transmission line 14 and the ground plane 34.
FIG. 2 shows a similar integrated circuit chip assembly portion to that shown in FIG. 1, except in FIG. 2 a substrate 40, made of gallium arsenide which is itself insulating, has deposited directly upon a first substrate surface 42 and within the substrate 40 an active electronic device 43 and a transmission line 44. The arrangement of the circuit lines and doped regions is similar to that described for FIG. 1 except the dielectric layer 20, in FIG. 1, is unnecessary and subsequently not included. Because of this exclusion, electrical insulation between the circuit lines of the electronic device 43 is accomplished by spacing the circuit lines apart over the first surface 42 of the substrate 40. Just as with the assembly in FIG. 1, a substrate second surface 45 contacts the surface of a ground plane 46.
FIG. 3 shows another existing design for the integrated circuit chip assembly. This arrangement is identical to that found in FIG. 1 except only a first surface 50 of the substrate 52 is planar. The second surface 54 of the substrate 52 has a concave shape in the region of the electronic device 12. A ground plane 56 contacts and conforms to the second surface 54 of the substrate 52. Through this configuration, the thermal resistance of the substrate 52 in the area of the electronic device 12 is reduced because the thickness of the substrate 52 in that region is reduced, and subsequently heat generated by the electronic device 12 may be more readily dissipated through the ground plane 56. Although not shown in FIG. 3, an enhancing modification to this design would involve the introduction of a thermally and electrically conducting via extending from the ground plane 56 through the substrate 52 to the electronic device 12 such that the thermal resistance of the substrate 52 is largely bypassed by the newly formed thermally conductive path to the ground plane 56 provided by the via. Ideally the via would physically contact the ground plane 56 and either the circuit line 26 (FIG. 1) of the source region 22 or the circuit line 30 of the drain region of the electronic device 12 24 to provide an electrical and thermal ground.
While the arrangement shown in FIG. 3 and the modification described do enhance the ability to dissipate heat from the electronic device 12, the process of forming a concave surface within the substrate 52 material in the region of the electronic device 12 is, in practice, very difficult. This is especially true with substrates made from gallium arsenide because that material is inherently brittle. Furthermore, while this does provide better heat dissipation to the electronic device 12, there is no relief provided to adjust the impedance of the transmission line 14 because the substrate 52 still must function to provide structural support to the entire integrated circuit chip assembly. Consequently the substrate 52 thickness in the region away from the electronic device 12 between the transmission line 14 and the ground plane 56 remains unchanged and the overall impedance generated by the inductance and capacitance of the transmission line therefore remains unchanged. Note the ground plane is not limited to acting as an electrical ground since it may just as easily provide current to components on the substrate.
Note that the same design discussed in FIG. 3 and the associated enhancement also apply to a chip assembly utilizing a substrate made of gallium arsenide. The difference would be the absence of the insulating layer and the direct deposition of circuit lines onto the gallium arsenide substrate surface. The remainder of the design would remain essentially the same.
It is an object of this invention to provide an integrated circuit chip assembly design that permits effective dissipation of heat generated by electronic devices of the assembly.
It is another object of this invention to provide an integrated circuit chip assembly design by which the assembly, is structurally supported in a manner not dependent on the thickness of the substrate.
It is still another object of this invention to provide an integrated circuit chip assembly design that permits adjustment of the impedance of the transmission lines through varying the distance from the transmission line to the ground plane.
It is yet another object of this invention to provide an integrated circuit chip assembly design that permits adjustment of the transmission line impedance through the selection of a dielectric substance for introduction between a transmission line and the ground plane.